/** @file
  This file provides common part for Gpio V2 Controller PEI and DXE modules

  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
  SPDX-License-Identifier: BSD-2-Clause-Patent

@par Specification Reference:
**/
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/CryptoLib.h>
#include <Library/BootloaderCommonLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/TpmLib.h>
#include <Library/PcdLib.h>
#include <Library/HobLib.h>
#include <Pi/PiBootMode.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciExpressLib.h>
#include <Library/SortLib.h>
#include <Library/MtlSocInfoLib.h>
#include <Library/MtlSocGpioTopologyLib.h>
#include <Include/GpioV2Pad.h>
#include <Register/GpioRegsVer6.h>
#include <Register/GpioV2ChipsetId.h>
#include <GpioV2PinsMtlSoc.h>
#include <Include/GpioV2ControllerInterface.h>
#include <Register/PmcRegsVer6.h>
#include <Library/DebugLib.h>
#include <Uefi/UefiBaseType.h>
#include <Include/RegisterAccess.h>
#include <Include/P2SbController.h>
#include <Include/PcrDefine.h>
#include <Library/PciSegmentLib.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Pi/PiBootMode.h>
#include <Library/PchInfoLib.h>
#include <Library/HobLib.h>
#include <Library/P2SbSocLib.h>

extern EFI_GUID gGpioV2UnlockDataHobGuidSoc0;


//*********************************************************************
//                    MTL-SOC-M Pins Start                            *
//*********************************************************************

//
// MTL-SOC-M
//
GPIOV2_PAD MtlSocMCommunity0Group0Pads[] = {
  GPIOV2_MTL_SOC_M_CPU_PECI,
  GPIOV2_MTL_SOC_M_CPU_RESET_B,
  GPIOV2_MTL_SOC_M_CPU_SOUT,
  GPIOV2_MTL_SOC_M_CPU_SCK,
  GPIOV2_MTL_SOC_M_CPU_ALERT_B
};

GPIOV2_PAD MtlSocMCommunity0Group1Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_V0,
  GPIOV2_MTL_SOC_M_GPP_V1,
  GPIOV2_MTL_SOC_M_GPP_V2,
  GPIOV2_MTL_SOC_M_GPP_V3,
  GPIOV2_MTL_SOC_M_GPP_V4,
  GPIOV2_MTL_SOC_M_GPP_V5,
  GPIOV2_MTL_SOC_M_GPP_V6,
  GPIOV2_MTL_SOC_M_GPP_V7,
  GPIOV2_MTL_SOC_M_GPP_V8,
  GPIOV2_MTL_SOC_M_GPP_V9,
  GPIOV2_MTL_SOC_M_GPP_V10,
  GPIOV2_MTL_SOC_M_GPP_V11,
  GPIOV2_MTL_SOC_M_GPP_V12,
  GPIOV2_MTL_SOC_M_GPP_V13,
  GPIOV2_MTL_SOC_M_GPP_V14,
  GPIOV2_MTL_SOC_M_GPP_V15,
  GPIOV2_MTL_SOC_M_GPP_V16,
  GPIOV2_MTL_SOC_M_GPP_V17,
  GPIOV2_MTL_SOC_M_GPP_V18,
  GPIOV2_MTL_SOC_M_GPP_V19,
  GPIOV2_MTL_SOC_M_GPP_V20,
  GPIOV2_MTL_SOC_M_GPP_V21,
  GPIOV2_MTL_SOC_M_GPP_V22,
  GPIOV2_MTL_SOC_M_GPP_V23
};

GPIOV2_PAD MtlSocMCommunity0Group2Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_C0,
  GPIOV2_MTL_SOC_M_GPP_C1,
  GPIOV2_MTL_SOC_M_GPP_C2,
  GPIOV2_MTL_SOC_M_GPP_C3,
  GPIOV2_MTL_SOC_M_GPP_C4,
  GPIOV2_MTL_SOC_M_GPP_C5,
  GPIOV2_MTL_SOC_M_GPP_C6,
  GPIOV2_MTL_SOC_M_GPP_C7,
  GPIOV2_MTL_SOC_M_GPP_C8,
  GPIOV2_MTL_SOC_M_GPP_C9,
  GPIOV2_MTL_SOC_M_GPP_C10,
  GPIOV2_MTL_SOC_M_GPP_C11,
  GPIOV2_MTL_SOC_M_GPP_C12,
  GPIOV2_MTL_SOC_M_GPP_C13,
  GPIOV2_MTL_SOC_M_GPP_C14,
  GPIOV2_MTL_SOC_M_GPP_C15,
  GPIOV2_MTL_SOC_M_GPP_C16,
  GPIOV2_MTL_SOC_M_GPP_C17,
  GPIOV2_MTL_SOC_M_GPP_C18,
  GPIOV2_MTL_SOC_M_GPP_C19,
  GPIOV2_MTL_SOC_M_GPP_C20,
  GPIOV2_MTL_SOC_M_GPP_C21,
  GPIOV2_MTL_SOC_M_GPP_C22,
  GPIOV2_MTL_SOC_M_GPP_C23
};

// Mtl Soc M Com 0
GPIOV2_GROUP MtlSocMCommunity0Groups[] = {
  {  /* Group CPU */
    .Name = "CPU",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_CPU,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_CPU, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_CPU },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_I_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_I_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_CPU_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity0Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity0Group0Pads,
    .PadDataArray = NULL
  },
  {  /* Group B */
    .Name = "GPP_V",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_V,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_V, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_V },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_I_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_I_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_V_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity0Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity0Group1Pads,
    .PadDataArray = NULL
  },
  { /* SPI */
    .Name = "GPP_C",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_C,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_C, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_C },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_PAD_OWN,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_PADCFGLOCK,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_PADCFGLOCKTX,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_HOSTSW_OWN,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_GPI_IS,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_GPI_IE,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_GPI_GPE_STS,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_GPI_GPE_EN,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_I_SMI_STS,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_I_SMI_EN,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_NMI_STS,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_NMI_EN,   R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_C_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity0Group2Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity0Group2Pads,
    .PadDataArray = NULL
  }
};

GPIOV2_PAD MtlSocMCommunity1Group0Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_A0,
  GPIOV2_MTL_SOC_M_GPP_A1,
  GPIOV2_MTL_SOC_M_GPP_A2,
  GPIOV2_MTL_SOC_M_GPP_A3,
  GPIOV2_MTL_SOC_M_GPP_A4,
  GPIOV2_MTL_SOC_M_GPP_A5,
  GPIOV2_MTL_SOC_M_GPP_A6,
  GPIOV2_MTL_SOC_M_GPP_A7,
  GPIOV2_MTL_SOC_M_GPP_A8,
  GPIOV2_MTL_SOC_M_GPP_A9,
  GPIOV2_MTL_SOC_M_GPP_A10,
  GPIOV2_MTL_SOC_M_GPP_A11,
  GPIOV2_MTL_SOC_M_GPP_A12,
  GPIOV2_MTL_SOC_M_GPP_A13,
  GPIOV2_MTL_SOC_M_GPP_A14,
  GPIOV2_MTL_SOC_M_GPP_A15,
  GPIOV2_MTL_SOC_M_GPP_A16,
  GPIOV2_MTL_SOC_M_GPP_A17,
  GPIOV2_MTL_SOC_M_GPP_A18,
  GPIOV2_MTL_SOC_M_GPP_A19,
  GPIOV2_MTL_SOC_M_GPP_A20,
  GPIOV2_MTL_SOC_M_GPP_A21,
  GPIOV2_MTL_SOC_M_GPP_A22,
  GPIOV2_MTL_SOC_M_GPP_A23,
  GPIOV2_MTL_SOC_M_ESPI_CLK_LOOPBK
};

GPIOV2_PAD MtlSocMCommunity1Group1Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_E0,
  GPIOV2_MTL_SOC_M_GPP_E1,
  GPIOV2_MTL_SOC_M_GPP_E2,
  GPIOV2_MTL_SOC_M_GPP_E3,
  GPIOV2_MTL_SOC_M_GPP_E4,
  GPIOV2_MTL_SOC_M_GPP_E5,
  GPIOV2_MTL_SOC_M_GPP_E6,
  GPIOV2_MTL_SOC_M_GPP_E7,
  GPIOV2_MTL_SOC_M_GPP_E8,
  GPIOV2_MTL_SOC_M_GPP_E9,
  GPIOV2_MTL_SOC_M_GPP_E10,
  GPIOV2_MTL_SOC_M_GPP_E11,
  GPIOV2_MTL_SOC_M_GPP_E12,
  GPIOV2_MTL_SOC_M_GPP_E13,
  GPIOV2_MTL_SOC_M_GPP_E14,
  GPIOV2_MTL_SOC_M_GPP_E15,
  GPIOV2_MTL_SOC_M_GPP_E16,
  GPIOV2_MTL_SOC_M_GPP_E17,
  GPIOV2_MTL_SOC_M_GPP_E18,
  GPIOV2_MTL_SOC_M_GPP_E19,
  GPIOV2_MTL_SOC_M_GPP_E20,
  GPIOV2_MTL_SOC_M_GPP_E21,
  GPIOV2_MTL_SOC_M_GPP_E22,
  GPIOV2_MTL_SOC_M_GPP_E23,
  GPIOV2_MTL_SOC_M_THC0_GPSI0_CLK_LOOPBK
};

//
// Mtl Soc M Com 1
//
GPIOV2_GROUP MtlSocMCommunity1Groups[] = {
  {  /* Group A */
    .Name = "GPP_A",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_A,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_A, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_A },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_A_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity1Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity1Group0Pads,
    .PadDataArray = NULL
  },
  {  /* Group E */
    .Name = "GPP_E",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_E,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_E, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_E },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_E_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity1Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity1Group1Pads,
    .PadDataArray = NULL
  }
};

//
// Mtl Soc M Com 2
//

//
// Mtl Soc M Com 3
//
GPIOV2_PAD MtlSocMCommunity3Group0Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_H0,
  GPIOV2_MTL_SOC_M_GPP_H1,
  GPIOV2_MTL_SOC_M_GPP_H2,
  GPIOV2_MTL_SOC_M_GPP_H3,
  GPIOV2_MTL_SOC_M_GPP_H4,
  GPIOV2_MTL_SOC_M_GPP_H5,
  GPIOV2_MTL_SOC_M_GPP_H6,
  GPIOV2_MTL_SOC_M_GPP_H7,
  GPIOV2_MTL_SOC_M_GPP_H8,
  GPIOV2_MTL_SOC_M_GPP_H9,
  GPIOV2_MTL_SOC_M_GPP_H10,
  GPIOV2_MTL_SOC_M_GPP_H11,
  GPIOV2_MTL_SOC_M_GPP_H12,
  GPIOV2_MTL_SOC_M_GPP_H13,
  GPIOV2_MTL_SOC_M_GPP_H14,
  GPIOV2_MTL_SOC_M_GPP_H15,
  GPIOV2_MTL_SOC_M_GPP_H16,
  GPIOV2_MTL_SOC_M_GPP_H17,
  GPIOV2_MTL_SOC_M_GPP_H18,
  GPIOV2_MTL_SOC_M_GPP_H19,
  GPIOV2_MTL_SOC_M_GPP_H20,
  GPIOV2_MTL_SOC_M_GPP_H21,
  GPIOV2_MTL_SOC_M_GPP_H22,
  GPIOV2_MTL_SOC_M_GPP_H23,
  GPIOV2_MTL_SOC_M_LPI3C1_CLK_LOOPBK,
  GPIOV2_MTL_SOC_M_LPI3C0_CLK_LOOPBK
};

GPIOV2_PAD MtlSocMCommunity3Group1Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_F0,
  GPIOV2_MTL_SOC_M_GPP_F1,
  GPIOV2_MTL_SOC_M_GPP_F2,
  GPIOV2_MTL_SOC_M_GPP_F3,
  GPIOV2_MTL_SOC_M_GPP_F4,
  GPIOV2_MTL_SOC_M_GPP_F5,
  GPIOV2_MTL_SOC_M_GPP_F6,
  GPIOV2_MTL_SOC_M_GPP_F7,
  GPIOV2_MTL_SOC_M_GPP_F8,
  GPIOV2_MTL_SOC_M_GPP_F9,
  GPIOV2_MTL_SOC_M_GPP_F10,
  GPIOV2_MTL_SOC_M_GPP_F11,
  GPIOV2_MTL_SOC_M_GPP_F12,
  GPIOV2_MTL_SOC_M_GPP_F13,
  GPIOV2_MTL_SOC_M_GPP_F14,
  GPIOV2_MTL_SOC_M_GPP_F15,
  GPIOV2_MTL_SOC_M_GPP_F16,
  GPIOV2_MTL_SOC_M_GPP_F17,
  GPIOV2_MTL_SOC_M_GPP_F18,
  GPIOV2_MTL_SOC_M_GPP_F19,
  GPIOV2_MTL_SOC_M_GPP_F20,
  GPIOV2_MTL_SOC_M_GPP_F21,
  GPIOV2_MTL_SOC_M_GPP_F22,
  GPIOV2_MTL_SOC_M_GPP_F23,
  GPIOV2_MTL_SOC_M_THC1_GSPI1_CLK_LOOPBK,
  GPIOV2_MTL_SOC_M_GSPI0A_CLK_LOOPBK
};

GPIOV2_PAD MtlSocMCommunity3Group2Pads[] = {
  GPIOV2_MTL_SOC_M_SPI0_IO2,
  GPIOV2_MTL_SOC_M_SPI0_IO3,
  GPIOV2_MTL_SOC_M_SPI0_MOSI_IO_0,
  GPIOV2_MTL_SOC_M_SPI0_MISO_IO_0,
  GPIOV2_MTL_SOC_M_SPI0_TPM_CS_B,
  GPIOV2_MTL_SOC_M_SPI0_FLASH_0_CS_B,
  GPIOV2_MTL_SOC_M_SPI0_FLASH_1_CS_B,
  GPIOV2_MTL_SOC_M_SPI0_CLK,
  GPIOV2_MTL_SOC_M_BKLTEN,
  GPIOV2_MTL_SOC_M_BKLTCTL,
  GPIOV2_MTL_SOC_M_VDDEN,
  GPIOV2_MTL_SOC_M_SYS_PWROK,
  GPIOV2_MTL_SOC_M_SYS_RESET_B,
  GPIOV2_MTL_SOC_M_MLK_RST_B,
  GPIOV2_MTL_SOC_M_SPI0_CLK_LOOPBK
};

GPIOV2_PAD MtlSocMCommunity3Group3Pads[] = {
  GPIOV2_MTL_SOC_M_USB_0,
  GPIOV2_MTL_SOC_M_USB_1,
  GPIOV2_MTL_SOC_M_USB_2,
  GPIOV2_MTL_SOC_M_USB_3,
  GPIOV2_MTL_SOC_M_USB_4,
  GPIOV2_MTL_SOC_M_USB_5,
  GPIOV2_MTL_SOC_M_USB_6,
  GPIOV2_MTL_SOC_M_USB_7,
  GPIOV2_MTL_SOC_M_TS_0,
  GPIOV2_MTL_SOC_M_TS_1,
  GPIOV2_MTL_SOC_M_THC_0,
  GPIOV2_MTL_SOC_M_THC_1,
  GPIOV2_MTL_SOC_M_THC_2,
  GPIOV2_MTL_SOC_M_THC_3
};

GPIOV2_GROUP MtlSocMCommunity3Groups[] = {
  {
    .Name = "GPP_H",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_H,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_H, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_H },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_H_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity3Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity3Group0Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "GPP_F",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_F,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_F, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_F },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_F_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity3Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity3Group1Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "SPI",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_SPI,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_SPI_SYS, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_SPI_SYS },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_PADCFG_OFFSET },
    .PadsNum = sizeof(MtlSocMCommunity3Group2Pads) / sizeof(GPIOV2_PAD),
    .Pads = MtlSocMCommunity3Group2Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "USB",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_USB,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_USB, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_USB },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_SPI_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity3Group3Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity3Group3Pads,
    .PadDataArray = NULL
  }
};

//
// Mtl Soc M Com 4
//
GPIOV2_PAD MtlSocMCommunity4Group0Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_S0,
  GPIOV2_MTL_SOC_M_GPP_S1,
  GPIOV2_MTL_SOC_M_GPP_S2,
  GPIOV2_MTL_SOC_M_GPP_S3,
  GPIOV2_MTL_SOC_M_GPP_S4,
  GPIOV2_MTL_SOC_M_GPP_S5,
  GPIOV2_MTL_SOC_M_GPP_S6,
  GPIOV2_MTL_SOC_M_GPP_S7
};

GPIOV2_PAD MtlSocMCommunity4Group1Pads[] = {
  GPIOV2_MTL_SOC_M_MBPB0,
  GPIOV2_MTL_SOC_M_MBPB1,
  GPIOV2_MTL_SOC_M_MBPB2,
  GPIOV2_MTL_SOC_M_MBPB3,
  GPIOV2_MTL_SOC_M_JTAG_TDO,
  GPIOV2_MTL_SOC_M_PRDY_B,
  GPIOV2_MTL_SOC_M_PREQ_B,
  GPIOV2_MTL_SOC_M_JTAG_TDI,
  GPIOV2_MTL_SOC_M_JTAG_TMS,
  GPIOV2_MTL_SOC_M_JTAG_TCK,
  GPIOV2_MTL_SOC_M_DBG_PMODE,
  GPIOV2_MTL_SOC_M_JTAG_TRST_B
};

GPIOV2_GROUP MtlSocMCommunity4Groups[] = {
  {
    .Name = "GPP_S",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_S,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_S, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_S },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_S_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity4Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity4Group0Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "JTAG",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_MBPB,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_JTAG, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_JTAG },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_JTAG_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity4Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity4Group1Pads,
    .PadDataArray = NULL
  }
};

//
// Mtl Soc M Com 5
//
GPIOV2_PAD MtlSocMCommunity5Group0Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_B0,
  GPIOV2_MTL_SOC_M_GPP_B1,
  GPIOV2_MTL_SOC_M_GPP_B2,
  GPIOV2_MTL_SOC_M_GPP_B3,
  GPIOV2_MTL_SOC_M_GPP_B4,
  GPIOV2_MTL_SOC_M_GPP_B5,
  GPIOV2_MTL_SOC_M_GPP_B6,
  GPIOV2_MTL_SOC_M_GPP_B7,
  GPIOV2_MTL_SOC_M_GPP_B8,
  GPIOV2_MTL_SOC_M_GPP_B9,
  GPIOV2_MTL_SOC_M_GPP_B10,
  GPIOV2_MTL_SOC_M_GPP_B11,
  GPIOV2_MTL_SOC_M_GPP_B12,
  GPIOV2_MTL_SOC_M_GPP_B13,
  GPIOV2_MTL_SOC_M_GPP_B14,
  GPIOV2_MTL_SOC_M_GPP_B15,
  GPIOV2_MTL_SOC_M_GPP_B16,
  GPIOV2_MTL_SOC_M_GPP_B17,
  GPIOV2_MTL_SOC_M_GPP_B18,
  GPIOV2_MTL_SOC_M_GPP_B19,
  GPIOV2_MTL_SOC_M_GPP_B20,
  GPIOV2_MTL_SOC_M_GPP_B21,
  GPIOV2_MTL_SOC_M_GPP_B22,
  GPIOV2_MTL_SOC_M_GPP_B23,
  GPIOV2_MTL_SOC_M_ISHI3C0_CLK_LOOPBK
};

GPIOV2_PAD MtlSocMCommunity5Group1Pads[] = {
  GPIOV2_MTL_SOC_M_GPP_D0,
  GPIOV2_MTL_SOC_M_GPP_D1,
  GPIOV2_MTL_SOC_M_GPP_D2,
  GPIOV2_MTL_SOC_M_GPP_D3,
  GPIOV2_MTL_SOC_M_GPP_D4,
  GPIOV2_MTL_SOC_M_GPP_D5,
  GPIOV2_MTL_SOC_M_GPP_D6,
  GPIOV2_MTL_SOC_M_GPP_D7,
  GPIOV2_MTL_SOC_M_GPP_D8,
  GPIOV2_MTL_SOC_M_GPP_D9,
  GPIOV2_MTL_SOC_M_GPP_D10,
  GPIOV2_MTL_SOC_M_GPP_D11,
  GPIOV2_MTL_SOC_M_GPP_D12,
  GPIOV2_MTL_SOC_M_GPP_D13,
  GPIOV2_MTL_SOC_M_GPP_D14,
  GPIOV2_MTL_SOC_M_GPP_D15,
  GPIOV2_MTL_SOC_M_GPP_D16,
  GPIOV2_MTL_SOC_M_GPP_D17,
  GPIOV2_MTL_SOC_M_GPP_D18,
  GPIOV2_MTL_SOC_M_GPP_D19,
  GPIOV2_MTL_SOC_M_GPP_D20,
  GPIOV2_MTL_SOC_M_GPP_D21,
  GPIOV2_MTL_SOC_M_GPP_D22,
  GPIOV2_MTL_SOC_M_GPP_D23,
  GPIOV2_MTL_SOC_M_BOOTHALT_B
};

GPIOV2_PAD MtlSocMCommunity5Group2Pads[] = {
  GPIOV2_MTL_SOC_M_VGPIO0,
  GPIOV2_MTL_SOC_M_VGPIO4,
  GPIOV2_MTL_SOC_M_VGPIO5,
  GPIOV2_MTL_SOC_M_VGPIO6,
  GPIOV2_MTL_SOC_M_VGPIO7,
  GPIOV2_MTL_SOC_M_VGPIO8,
  GPIOV2_MTL_SOC_M_VGPIO9,
  GPIOV2_MTL_SOC_M_VGPIO10,
  GPIOV2_MTL_SOC_M_VGPIO11,
  GPIOV2_MTL_SOC_M_VGPIO12,
  GPIOV2_MTL_SOC_M_VGPIO13,
  GPIOV2_MTL_SOC_M_VGPIO18,
  GPIOV2_MTL_SOC_M_VGPIO19,
  GPIOV2_MTL_SOC_M_VGPIO20,
  GPIOV2_MTL_SOC_M_VGPIO21,
  GPIOV2_MTL_SOC_M_VGPIO22,
  GPIOV2_MTL_SOC_M_VGPIO23,
  GPIOV2_MTL_SOC_M_VGPIO24,
  GPIOV2_MTL_SOC_M_VGPIO25,
  GPIOV2_MTL_SOC_M_VGPIO30,
  GPIOV2_MTL_SOC_M_VGPIO31,
  GPIOV2_MTL_SOC_M_VGPIO32,
  GPIOV2_MTL_SOC_M_VGPIO33,
  GPIOV2_MTL_SOC_M_VGPIO34,
  GPIOV2_MTL_SOC_M_VGPIO35,
  GPIOV2_MTL_SOC_M_VGPIO36,
  GPIOV2_MTL_SOC_M_VGPIO37,
  GPIOV2_MTL_SOC_M_VGPIO40,
  GPIOV2_MTL_SOC_M_VGPIO41,
  GPIOV2_MTL_SOC_M_VGPIO42,
  GPIOV2_MTL_SOC_M_VGPIO43,
  GPIOV2_MTL_SOC_M_VGPIO44,
  GPIOV2_MTL_SOC_M_VGPIO45,
  GPIOV2_MTL_SOC_M_VGPIO46,
  GPIOV2_MTL_SOC_M_VGPIO47
};

GPIOV2_GROUP MtlSocMCommunity5Groups[] = {
  {
    .Name = "GPP_B",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_B,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_B, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_B },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_B_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity5Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity5Group0Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "GPP_D",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_D,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_GPP_D, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_GPP_D },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_GPP_D_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity5Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity5Group1Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "VGPIO",
    .GpioPadGroup = GPIOV2_MTL_SOC_M_GROUP_VGPIO,
    .GroupToGpeMapping = { V_MTL_SOC_M_PMC_PWRM_GPIO_CFG_VGPIO, V_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG_GPE0_VGPIO },
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_PAD_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_VPGIO5_PADCFGLOCK, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_PADCFGLOCKTX, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_HOSTSW_OWN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_GPI_IS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_GPI_IE, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_GPI_GPE_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_GPI_GPE_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_SMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_SMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_NMI_STS, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_NMI_EN, R_GPIO_VER6_SOC_M_GPIO_PCR_VGPIO5_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocMCommunity5Group2Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocMCommunity5Group2Pads,
    .PadDataArray = NULL
  }
};

GPIOV2_COMMUNITY MtlSocMCommunities[] = {
  {
    // COM 0
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocMCommunity0Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocMCommunity0Groups
  },
  {
    // COM 1
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocMCommunity1Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocMCommunity1Groups
  },
    // COM 2
  {
    // COM 3
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocMCommunity3Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocMCommunity3Groups
  },
  {
    // COM 4
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocMCommunity4Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocMCommunity4Groups
  },
  {
    // COM 5
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocMCommunity5Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocMCommunity5Groups
  }
};
//*********************************************************************
//                    MTL-SOC-M Pins End                              *
//*********************************************************************

//*********************************************************************
//                    MTL-SOC-S Pins Start                            *
//*********************************************************************

GPIOV2_PAD MtlSocSCommunity0Group0Pads[] = {
  GPIOV2_MTL_SOC_S_GPP_A0,
  GPIOV2_MTL_SOC_S_GPP_A1,
  GPIOV2_MTL_SOC_S_GPP_A2,
  GPIOV2_MTL_SOC_S_GPP_A3,
  GPIOV2_MTL_SOC_S_GPP_A4,
  GPIOV2_MTL_SOC_S_GPP_A5,
  GPIOV2_MTL_SOC_S_GPP_A6,
  GPIOV2_MTL_SOC_S_GPP_A7,
  GPIOV2_MTL_SOC_S_GPP_A8,
  GPIOV2_MTL_SOC_S_GPP_A9,
  GPIOV2_MTL_SOC_S_GPP_A10,
  GPIOV2_MTL_SOC_S_GPP_A11,
  GPIOV2_MTL_SOC_S_GPP_A12,
  GPIOV2_MTL_SOC_S_GPP_A13,
  GPIOV2_MTL_SOC_S_GPP_A14,
  GPIOV2_MTL_SOC_S_GPP_A15,
  GPIOV2_MTL_SOC_S_GPP_A16,
  GPIOV2_MTL_SOC_S_GPP_A17,
  GPIOV2_MTL_SOC_S_GPP_A18,
  GPIOV2_MTL_SOC_S_GPP_A19,
  GPIOV2_MTL_SOC_S_GPP_A20,
  GPIOV2_MTL_SOC_S_GPP_A21,
  GPIOV2_MTL_SOC_S_GPP_A22,
  GPIOV2_MTL_SOC_S_GPP_A23,
  GPIOV2_MTL_SOC_S_RTCCLKIN,
  GPIOV2_MTL_SOC_S_RESET_SYNC_B,
  GPIOV2_MTL_SOC_S_PCH_PWROK,
  GPIOV2_MTL_SOC_S_ESPI_CLK_LOOPBACK
};

GPIOV2_PAD MtlSocSCommunity0Group1Pads[] = {
  GPIOV2_MTL_SOC_S_VGPIO_LPC_0,
  GPIOV2_MTL_SOC_S_VGPIO_LPC_1,
  GPIOV2_MTL_SOC_S_VGPIO_LPC_2,
  GPIOV2_MTL_SOC_S_VGPIO_LPC_3,
  GPIOV2_MTL_SOC_S_VGPIO_LPC_4,
  GPIOV2_MTL_SOC_S_VGPIO_EC_SCI,
  GPIOV2_MTL_SOC_S_VGPIO_EC_SCI1
};

GPIOV2_PAD MtlSocSCommunity0Group2Pads[] = {
  GPIOV2_MTL_SOC_S_GPP_C0,
  GPIOV2_MTL_SOC_S_GPP_C1,
  GPIOV2_MTL_SOC_S_GPP_C2,
  GPIOV2_MTL_SOC_S_GPP_C3,
  GPIOV2_MTL_SOC_S_GPP_C4,
  GPIOV2_MTL_SOC_S_GPP_C5,
  GPIOV2_MTL_SOC_S_GPP_C6,
  GPIOV2_MTL_SOC_S_GPP_C7,
  GPIOV2_MTL_SOC_S_GPP_C8,
  GPIOV2_MTL_SOC_S_GPP_C9,
  GPIOV2_MTL_SOC_S_GPP_C10,
  GPIOV2_MTL_SOC_S_GPP_C11,
  GPIOV2_MTL_SOC_S_GPP_C12,
  GPIOV2_MTL_SOC_S_GPP_C13,
  GPIOV2_MTL_SOC_S_GPP_C14,
  GPIOV2_MTL_SOC_S_GPP_C15,
  GPIOV2_MTL_SOC_S_GPP_C16,
  GPIOV2_MTL_SOC_S_GPP_C17,
  GPIOV2_MTL_SOC_S_GPP_C18,
  GPIOV2_MTL_SOC_S_GPP_C19,
  GPIOV2_MTL_SOC_S_GPP_C20,
  GPIOV2_MTL_SOC_S_GPP_C21,
  GPIOV2_MTL_SOC_S_GPP_C22,
  GPIOV2_MTL_SOC_S_GPP_C23,
  GPIOV2_MTL_SOC_S_GPP_C24,
  GPIOV2_MTL_SOC_S_GPP_C25,
  GPIOV2_MTL_SOC_S_GPP_C26
};

// Mtl Soc S Com 0
GPIOV2_GROUP MtlSocSCommunity0Groups[] = {
  {  /* Group GPP A */
    .Name = "GPP_A",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_A,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_GPP_A, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_GPP_A },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_A_PADCFG_OFFSET },
    .PadsNum = sizeof(MtlSocSCommunity0Group0Pads) / sizeof(GPIOV2_PAD),
    .Pads = MtlSocSCommunity0Group0Pads,
    .PadDataArray = NULL
  },
  {  /* Group VGPIO LPC*/
    .Name = "VPGIO_LPC",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_VGPIO0,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_VGPIO_0, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_VGPIO_0 },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_0_PADCFG_OFFSET },
    .PadsNum = sizeof(MtlSocSCommunity0Group1Pads) / sizeof(GPIOV2_PAD),
    .Pads = MtlSocSCommunity0Group1Pads,
    .PadDataArray = NULL
  },
  { /* GPP C */
    .Name = "GPP_C",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_C,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_GPP_C, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_GPP_C },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_PAD_OWN,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_PADCFGLOCK,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_PADCFGLOCKTX,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_HOSTSW_OWN,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_GPI_IS,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_GPI_IE,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_GPI_GPE_STS,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_GPI_GPE_EN,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_SMI_STS,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_SMI_EN,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_NMI_STS,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_NMI_EN,   R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_C_PADCFG_OFFSET },
    .PadsNum = sizeof(MtlSocSCommunity0Group2Pads) / sizeof(GPIOV2_PAD),
    .Pads = MtlSocSCommunity0Group2Pads,
    .PadDataArray = NULL
  }
};

GPIOV2_PAD MtlSocSCommunity1Group0Pads[] = {
  GPIOV2_MTL_SOC_S_GPP_B0,
  GPIOV2_MTL_SOC_S_GPP_B1,
  GPIOV2_MTL_SOC_S_GPP_B2,
  GPIOV2_MTL_SOC_S_GPP_B3,
  GPIOV2_MTL_SOC_S_GPP_B4,
  GPIOV2_MTL_SOC_S_GPP_B5,
  GPIOV2_MTL_SOC_S_GPP_B6,
  GPIOV2_MTL_SOC_S_GPP_B7,
  GPIOV2_MTL_SOC_S_GPP_B8,
  GPIOV2_MTL_SOC_S_GPP_B9,
  GPIOV2_MTL_SOC_S_GPP_B10,
  GPIOV2_MTL_SOC_S_GPP_B11,
  GPIOV2_MTL_SOC_S_GPP_B12,
  GPIOV2_MTL_SOC_S_GPP_B13,
  GPIOV2_MTL_SOC_S_GPP_B14,
  GPIOV2_MTL_SOC_S_GPP_B15,
  GPIOV2_MTL_SOC_S_GPP_B16,
  GPIOV2_MTL_SOC_S_GPP_B17,
  GPIOV2_MTL_SOC_S_GPP_B18,
  GPIOV2_MTL_SOC_S_GPP_B19
};

GPIOV2_PAD MtlSocSCommunity1Group1Pads[] = {
  GPIOV2_MTL_SOC_S_VGPIO_USB_0,
  GPIOV2_MTL_SOC_S_VGPIO_USB_1,
  GPIOV2_MTL_SOC_S_VGPIO_USB_2,
  GPIOV2_MTL_SOC_S_VGPIO_USB_3,
  GPIOV2_MTL_SOC_S_VGPIO_PCIE_80,
  GPIOV2_MTL_SOC_S_VGPIO_TS_0,
  GPIOV2_MTL_SOC_S_VGPIO_TS_1
};

GPIOV2_PAD MtlSocSCommunity1Group2Pads[] = {
  GPIOV2_MTL_SOC_S_GPP_D0,
  GPIOV2_MTL_SOC_S_GPP_D1,
  GPIOV2_MTL_SOC_S_GPP_D2,
  GPIOV2_MTL_SOC_S_GPP_D3,
  GPIOV2_MTL_SOC_S_GPP_D4,
  GPIOV2_MTL_SOC_S_GPP_D5,
  GPIOV2_MTL_SOC_S_GPP_D6,
  GPIOV2_MTL_SOC_S_GPP_D7,
  GPIOV2_MTL_SOC_S_GPP_D8,
  GPIOV2_MTL_SOC_S_GPP_D9,
  GPIOV2_MTL_SOC_S_GPP_D10,
  GPIOV2_MTL_SOC_S_GPP_D11,
  GPIOV2_MTL_SOC_S_GPP_D12,
  GPIOV2_MTL_SOC_S_GPP_D13,
  GPIOV2_MTL_SOC_S_GPP_D14,
  GPIOV2_MTL_SOC_S_GPP_D15,
  GPIOV2_MTL_SOC_S_GPP_D16,
  GPIOV2_MTL_SOC_S_GPP_D17,
  GPIOV2_MTL_SOC_S_GPP_D18,
  GPIOV2_MTL_SOC_S_GPP_D19,
  GPIOV2_MTL_SOC_S_GPP_D20,
  GPIOV2_MTL_SOC_S_GPP_D21,
  GPIOV2_MTL_SOC_S_GPP_D22,
  GPIOV2_MTL_SOC_S_GPP_D23
};
//
// Mtl Soc S Com 1
//
GPIOV2_GROUP MtlSocSCommunity1Groups[] = {
  {  /* Group B */
    .Name = "GPP_B",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_B,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_GPP_B, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_GPP_B },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_B_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocSCommunity1Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocSCommunity1Group0Pads,
    .PadDataArray = NULL
  },
  {  /* Group VGPIO */
    .Name = "VGPIO_USB",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_VGPIO3,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_VGPIO_3, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_VGPIO_3 },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_3_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocSCommunity1Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocSCommunity1Group1Pads,
    .PadDataArray = NULL
  },
  {  /* Group D */
    .Name = "GPP_D",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_D,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_GPP_D, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_GPP_D },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_GPP_D_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocSCommunity1Group2Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocSCommunity1Group2Pads,
    .PadDataArray = NULL
  }
};

//
// Mtl Soc S Com 3
//
GPIOV2_PAD MtlSocSCommunity3Group0Pads[] = {
  GPIOV2_MTL_SOC_S_PECI,
  GPIOV2_MTL_SOC_S_VIDSOUT,
  GPIOV2_MTL_SOC_S_VIDSCK,
  GPIOV2_MTL_SOC_S_VIDALERT_B,
  GPIOV2_MTL_SOC_S_JTAG_MBPB_0,
  GPIOV2_MTL_SOC_S_JTAG_MBPB_1,
  GPIOV2_MTL_SOC_S_JTAG_MBPB_2,
  GPIOV2_MTL_SOC_S_JTAG_MBPB_3,
  GPIOV2_MTL_SOC_S_JTAG_TDO,
  GPIOV2_MTL_SOC_S_PRDY_B,
  GPIOV2_MTL_SOC_S_PREQ_B,
  GPIOV2_MTL_SOC_S_JTAG_TDI,
  GPIOV2_MTL_SOC_S_JTAG_TMS,
  GPIOV2_MTL_SOC_S_JTAG_TCK,
  GPIOV2_MTL_SOC_S_JTAG_PMODE,
  GPIOV2_MTL_SOC_S_JTAG_TRST_B
};

GPIOV2_PAD MtlSocSCommunity3Group1Pads[] = {
  GPIOV2_MTL_SOC_S_VGPIO_ISCLK0,
  GPIOV2_MTL_SOC_S_VGPIO_ISCLK1
};

GPIOV2_GROUP MtlSocSCommunity3Groups[] = {
  {
    .Name = "JTAG",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_JTAG,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_JTAG, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_JTAG },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_JTAG_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocSCommunity3Group0Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocSCommunity3Group0Pads,
    .PadDataArray = NULL
  },
  {
    .Name = "VGPIO_ISCLK",
    .GpioPadGroup = GPIOV2_MTL_SOC_S_GROUP_VGPIO4,
    .GroupToGpeMapping = { V_MTL_SOC_S_PMC_PWRM_GPIO_CFG_VGPIO_4, V_GPIO_VER6_SOC_S_GPIO_PCR_MISCCFG_GPE0_VGPIO_4 },
    .RegisterOffsets = { R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_PAD_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_PADCFGLOCK, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_PADCFGLOCKTX, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_HOSTSW_OWN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_GPI_IS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_GPI_IE, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_GPI_GPE_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_GPI_GPE_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_SMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_SMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_NMI_STS, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_NMI_EN, R_GPIO_VER6_SOC_S_GPIO_PCR_VGPIO_4_PADCFG_OFFSET },
    .PadsNum = sizeof (MtlSocSCommunity3Group1Pads) / sizeof (GPIOV2_PAD),
    .Pads = MtlSocSCommunity3Group1Pads,
    .PadDataArray = NULL
  }
};

GPIOV2_COMMUNITY MtlSocSCommunities[] = {
  {
    // COM 0
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocSCommunity0Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocSCommunity0Groups
  },
  {
    // COM 1
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocSCommunity1Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocSCommunity1Groups
  },
  // COM 2
  {
    // COM 3
    .RegisterOffsets = { R_GPIO_VER6_SOC_M_GPIO_PCR_MISCCFG, R_GPIO_VER6_SOC_M_GPIO_PCR_G0_RCP_DW0 },
    .GroupsNum = sizeof (MtlSocSCommunity3Groups) / sizeof (GPIOV2_GROUP),
    .Groups = MtlSocSCommunity3Groups
  }
  // COM 4
  // COM 5
};
//*********************************************************************
//                    MTL-SOC-S Pins Start                            *
//*********************************************************************

/**
  This procedure retrieves number of communities for PCH with index 'PchIndex'

  @param[in] PchIndex             MTL SOC/PCH index

  @retval                         Number of communities on requested PCH
**/
UINT32
MtlSocGpioGetCommunitiesNum (
  IN UINT32 PchIndex
  )
{
  if (MtlIsSocM ()) {
    return sizeof (MtlSocMCommunities) / sizeof (GPIOV2_COMMUNITY);       // Mtl Soc M
  }
  return sizeof (MtlSocSCommunities) / sizeof (GPIOV2_COMMUNITY);         // Mtl Soc S
}

/**
  This procedure retrieves pointer to array of communities for PCH with index 'PchIndex'

  @param[in] PchIndex             MTL SOC/PCH index

  @retval                         pointer to array of communities on requested PCH
**/
GPIOV2_COMMUNITY*
MtlSocGpioGetCommunities (
  IN UINT32 PchIndex
  )
{
  if (MtlIsSocM ()) {
    return MtlSocMCommunities;       // Mtl Soc M
  }
  return MtlSocSCommunities;         // Mtl Soc S
}

/**
  This procedure retrieves pointer to community for PCH with community index.

  @param[in] CommunityIndex       Community Index

  @retval                         Pointer to community on requested Index
**/
GPIOV2_COMMUNITY*
MtlSocGpioGetCommunity (
    IN UINT32 CommunityIndex
  )
{
  if (MtlIsSocM ()) {
    return &(MtlSocMCommunities[CommunityIndex]);       // Mtl Soc M
  }
  return &(MtlSocSCommunities[CommunityIndex]);         // Mtl Soc S
}

/**
  This procedure retrieves number of communities for PCH with index 'PchIndex'

  @param[in] PchIndex             MTL SOC/PCH index

  @retval                         Number of communities on requested PCH
**/
GPIOV2_GROUP
MtlSocGpioGetGroups (
  IN UINT32 CommunityIndex,
  IN UINT32 GroupIndex
  )
{
  if (CommunityIndex == 0) {
    return (MtlSocMCommunity0Groups[GroupIndex]);
  }
  else if (CommunityIndex == 1) {
    return (MtlSocMCommunity1Groups[GroupIndex]);
  }
  else if (CommunityIndex == 2) {
    return (MtlSocMCommunity3Groups[GroupIndex]);
  }
  else if (CommunityIndex == 3) {
    return (MtlSocMCommunity4Groups[GroupIndex]);
  }
  else if (CommunityIndex == 4) {
    return (MtlSocMCommunity5Groups[GroupIndex]);
  } else {
    return (MtlSocMCommunity0Groups[GroupIndex]);
  }
  //return ((MtlSocGpioGetCommunities[CommunityIndex])[GroupIndex]);
}

EFI_STATUS
MtlSocInstallCommunityAccess (
 OUT P2SB_SIDEBAND_REGISTER_ACCESS   *CommunityAccess
)
{
  EFI_STATUS                          Status;
  UINT32                              CommunityIndex;
  P2SB_CONTROLLER                     P2SbController;

  CommunityAccess            = (P2SB_SIDEBAND_REGISTER_ACCESS *) AllocateZeroPool (sizeof (P2SB_SIDEBAND_REGISTER_ACCESS) * MtlSocGpioGetCommunitiesNum(0));

  Status = MtlSocGetP2SbController (&P2SbController);
  if (Status != EFI_SUCCESS) {
    ASSERT (FALSE);
  }

  for (CommunityIndex = 0; CommunityIndex < MtlSocGpioGetCommunitiesNum(0); CommunityIndex++) {
    BuildP2SbSidebandAccess (
      &P2SbController,
      (P2SB_PID)(MTL_SOC_PID_GPIOCOM0 + CommunityIndex),
      0,
      P2SbMemory,
      P2SbMmioAccess,
      TRUE,
      &(CommunityAccess[CommunityIndex])
      );
  }
  (VOID) PcdSet32S (PcdP2sb0Ptr, (UINT32)(UINTN)&(CommunityAccess[0]));
  (VOID) PcdSet32S (PcdP2sb1Ptr, (UINT32)(UINTN)&(CommunityAccess[1]));
  (VOID) PcdSet32S (PcdP2sb2Ptr, (UINT32)(UINTN)&(CommunityAccess[2]));
  (VOID) PcdSet32S (PcdP2sb3Ptr, (UINT32)(UINTN)&(CommunityAccess[3]));
  (VOID) PcdSet32S (PcdP2sb4Ptr, (UINT32)(UINTN)&(CommunityAccess[4]));
  return EFI_SUCCESS;
}

/**
  This procedure retrieves register offset for given Gpio Pad

  @param[in]  GpioPad             Gpio Pad. Please refer to GpioPinsYYY.h - where YYY name of the platform (eg. MTL, EBG, ...)
  @param[in]  Register            Register for which user want to retrieve offset. Please refer to GpioV2Pad.h
  @param[out] RegisterOffset      Pointer to a buffer for register offset

  @retval EFI_SUCCESS             The function completed successfully
  @retval EFI_INVALID_PARAMETER   Invalid group or pad number
**/
EFI_STATUS
MtlSocGpioGetRegOffset (
  IN  GPIOV2_PAD          GpioPad,
  IN  GPIOV2_REGISTER     Register,
  OUT UINT32              *RegisterOffset
  )
{
  GPIOV2_COMMUNITY   *Community;
  UINT32             CommunityIndex;
  UINT32             GroupIndex;
  UINT32             PadIndex;

  CommunityIndex = GPIOV2_PAD_GET_COMMUNITY_INDEX (GpioPad);
  GroupIndex     = GPIOV2_PAD_GET_GROUP_INDEX (GpioPad);
  PadIndex       = GPIOV2_PAD_GET_PAD_INDEX (GpioPad);

  Community = MtlSocGpioGetCommunity (CommunityIndex);

  switch (Register) {
    case GpioV2PadOwnReg:
      *RegisterOffset = Community->Groups[GroupIndex].RegisterOffsets.PadOwn + (PadIndex / 8) * 0x04;
      break;
    case GpioV2PadHostOwnReg:
      *RegisterOffset = Community->Groups[GroupIndex].RegisterOffsets.HostOwn;
      break;
    case GpioV2Dw0Reg:
      *RegisterOffset = Community->Groups[GroupIndex].RegisterOffsets.Dw0 + PadIndex * 0x10;
      break;
    case GpioV2Dw1Reg:
      *RegisterOffset = Community->Groups[GroupIndex].RegisterOffsets.Dw0 + 0x04 + PadIndex * 0x10;
      break;
    case GpioV2Dw2Reg:
      *RegisterOffset = Community->Groups[GroupIndex].RegisterOffsets.Dw0 + 0x08 + PadIndex * 0x10;
      break;
    default:
      return EFI_INVALID_PARAMETER;
  }
  return EFI_SUCCESS;
}
